In applications with non-volatile memory units charge pumps are typically used to provide a stable high-voltage level that is required to enable writing—or erasing—operations of the memory unit. For supplying a stable and constant voltage level, such charge pumps typically require regulation. In the absence of effective regulation the charge pump's output voltage may vary depending upon environmental conditions, electric load and the processing parameters under which the charge pump was fabricated. Among a variety of regulating circuits capacitive dividers are widely used, by way of which a high voltage level on the output of the charge pump can be sensed in the absence of any static current load. The capacitive divider is operable to divide the high voltage to levels which can be processed by a regulation or feedback loop that is typically operable to compare the downscaled voltage with a reference voltage.
In FIG. 1 a voltage regulator 1 with a capacitive divider 2 as it is widely known in the prior art is illustrated. Between the two capacitors 4, 6 of the capacitive divider 2 there is provided a sampling node 8 that forms an output 5 of the voltage regulator 1. Said output 5 is connected to an input of a comparator (not illustrated) to compare the voltage level of the sampling node 8 with a given reference voltage. Depending on this comparison, a voltage supply, typically in form of a charge pump is driven by the comparator to either increase or to decrease the voltage at the high voltage output 7.
At the beginning of a sampling operation the voltage regulator 1 needs to be initialized to start from well-defined conditions. For activating a reset mode, a switch 3 is closed while the capacitive voltage divider 2 is de-connected from the high voltage output 7. When operating the voltage regulator 1 in a sampling mode, the switch 3 is disconnected but since there is an inevitable current leakage across the switch 3, the voltage on the sampling node 8 will be influenced and may cause a drift of the output voltage as the voltage regulator 1.
This drawback is also described in US 2009/0059629 A1. There, a separate reset circuit is provided designed to reduce sample drift by reducing charge leakage from the sampling node.
Moreover, such voltage regulators 1 further comprise an inevitable parasitic capacitance on the output of the divider 2 that may vary with time, external or environmental conditions as well as with the electrical parameters at which the voltage regulator 1 is driven. The parasitic capacitance 9 may effectively vary the ratio of the capacitance of first and second capacitors 4, 6, thereby modifying the division ratio of the capacitive divider 2.
Generally, by increasing the capacitance of first and second capacitors 4, 6, the influence of a parasitic capacitance 9 may be reduced at the expense of comparatively large, bulky and expensive first and second capacitors 4, 6.